This invention relates to multilayer ceramic substrates, and more particularly relates to multilayer ceramic substrates having a sealed layer which are useful for electronics packaging and to a method for making such substrates.
Glass, ceramic and glass ceramic (hereinafter just ceramic) structures, usually and preferably multilayered, are used in the production of electronic substrates and devices. Many different types of structures can be used, and a few of these structures are described below. For example, a multilayered ceramic circuit substrate may comprise patterned metal layers which act as electrical conductors sandwiched between ceramic layers which act as insulators The substrates may be designed with termination pads for attaching semiconductor chips, connector leads, capacitors, resistors, covers, etc. Interconnection between buried conductor levels can be achieved through vias formed by metal paste-filled holes in the individual ceramic layers formed prior to lamination, which, upon sintering will become a sintered dense metal interconnection of metal based conductor.
In general, conventional ceramic structures are formed from ceramic green sheets which are prepared by mixing a ceramic particulate, a binder, plasticizers and solvents. This composition is spread or cast into ceramic sheets or slips from which the solvents are subsequently volatilized to provide coherent and self-supporting flexible green sheets. After blanking, via formation, stacking and laminating, the green sheet laminates are eventually fired at temperatures sufficient to drive off the binder resin and sinter the ceramic particulates together into a densified ceramic substrate.
Present state-of-the-art ceramic substrates are made from cordierite glass-ceramic particulate materials such as that disclosed in Kumar et al. U.S. Pat. No. 4,301,324, the disclosure of which is incorporated by reference herein. These substrates exhibit a dielectric constant of about 5 and a coefficient of thermal expansion (CTE) that closely matches that of silicon. It is desirable to fabricate substrates out of low dielectric constant materials so as to increase signal propagation speed, which varies inversely with the square root of the dielectric constant. The electrical conductors suitable for use with such glass-ceramic materials include copper and its alloys, silver and its alloys, and gold and its alloys.
It has been found by others that the vias do not completely seal to the ceramic material, thereby possibly resulting in a gap between the metallic via and the ceramic bulk material. This gap is undesirable as it reduces the hermeticity of the fabricated substrate as well as allowing fluids to seep into the substrate during processing. Accordingly, it has been proposed in Farooq et al., U.S. Pat. No. 5,073,180, the disclosure of which is incorporated by reference herein, to seal at least the top layer of a multilayer ceramic substrate with a composite via material consisting of metallic and ceramic (including glass) materials. The internal vias are essentially all metal. As taught by Siuta U.S. Pat. No. 4,594,181, the disclosure of which is incorporated by reference herein, the internal vias may also include small amounts of alumina or other ingredients to inhibit the densification of the metallic via.
At the interface between the composite sealing via and the metallic internal via, and/or at the interface between the internal via and the bulk ceramic, there is a mismatch of coefficients of thermal expansion and some difference in densification behavior during cofiring which makes the interface susceptible to fatigue failure when the substrate is exposed to thermal stress. The result is that an unrepairable open may occur at one of the above interfaces. If the net containing the open cannot be rerouted, the entire substrate must be scrapped. To alleviate the mismatch in coefficients of thermal expansion between the various vias, Knickerbocker et al. U.S. Pat. No. 5,293,504, the disclosure of which is incorporated by reference herein, have proposed capping the vias with a composite material comprising metallic and ceramic materials.
As an alternative to sealing the vias, a thin film sealing layer can be deposited on the surface of the ceramic substrate such as that disclosed in Boss et al. U.S. Pat. No. 4,880,684, the disclosure of which is incorporated by reference herein.
It is desirable to have a low TCE ceramic substrate that is of lower cost and easier manufacture.
Thin films beside being complicated to manufacture also dramatically increase the cost of manufacture of the ceramic substrate.
The various methods disclosed above that propose sealing the vias have worked well in practice. However, the present inventors have determined that due to the composite nature of the sealed via, there is a weaker bond to a joined chip than if the via was 100% metal. Too, the fact that the composite via contains a non-wettable ceramic material, plated metal and solder only adheres to the metallic portion of the via, thereby reducing the wettable area of the via.
It would be desirable to have a ceramic substrate having vias that are sealed and yet are easily joined to a chip or other device.
Accordingly, it is a purpose of the present invention to have a ceramic substrate with a sealed via layer to provide necessary hermeticity to the ceramic substrate.
It is another purpose of the present invention to have a via for joining to a chip or other device that is both wettable by plating and solder and that provides good chip pull strength.
These and other purposes of the present invention will become more apparent after referring to the following description of the invention considered in conjunction with the accompanying drawings.